Traditionally, performing a floating point mathematical operation and normalizing the result is a slow and tedious process. After computational circuitry performs a floating point operation on two operands, the result must be normalized so as to contain a "one" in the most significant bit (MSB) of the mantissa. A leading zero counter (LZC) or one detector is often used to count the number of leading zeroes in the mantissa. The floating point result is normalized by shifting the mantissa the number of bits indicated by the LZC. The result must also be converted to a signed magnitude form and rounded to ensure sufficient accuracy and precision. Typically, the steps of converting and rounding require two separate passes through an adder circuit.
Both computation and normalization steps are time consuming. The computation step is delayed due to the carry propagation of data during the floating point operation. In prior art systems, the normalization process cannot begin until after the floating point operation is complete. Current arithmetic systems are thus inherently slow since the computation and normalization steps must be performed sequentially.
Therefore, a need has arisen for an apparatus and method for increasing the speed of an arithmetic system by allowing normalization and computational functions to occur simultaneously.